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CS5342 105 dB, 192 kHz, Multi-bit Audio A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture 24-bit Conversion Supports all audio sample rates including 192 kHz. 105 dB Dynamic Range at 5 V -98 dB THD+N High-pass Filter to Remove DC Offsets Analog/Digital Core Supplies From 3.3 V to 5 V Supports logic levels between 2.5 V and 5 V. Low-latency Digital Filter Automatic Mode Selection Supports 384x MCLK/LRCK Ratios.
General Description
The CS5342 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analog-todigital conversion and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 200 kHz per channel. The CS5342 uses a 5th-order, multi-bit Delta-Sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The CS5342 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as set-top boxes, DVD-karaoke players, DVD recorders, A/V receivers, and automotive applications. ORDERING INFORMATION
CS5342-CZZ Lead-free CS5342-DZZ Lead-free CDB5342 -10 to 70 C -40 to 85 C 16-pin TSSOP 16-pin TSSOP Evaluation Board
VQ
REFGND
VL 2.5V - 5.0V SCLK LRCK SDOUT
MCLK
FILT+
Voltage Reference
Serial Output Interface
RST M0 M1
AINL S/H
+ -
LP Filter
Q
Digital Decimation Filter
High Pass Filter
DAC AINR S/H DAC + LP Filter Q Digital Decimation Filter High Pass Filter
VA 3.3V - 5.0V
GND
VD 3.3V - 5.0V
Preliminary Product Information
www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2004 (All Rights Reserved)
(c)
AUG `04 DS608PP2
CS5342
TABLE OF CONTENTS
1 CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 4 SPECIFIED OPERATING CONDITIONS ................................................................................. 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4 ANALOG CHARACTERISTICS (CS5342-CZZ) ....................................................................... 5 DIGITAL FILTER CHARACTERISTICS.................................................................................... 7 DC ELECTRICAL CHARACTERISTICS................................................................................. 10 DIGITAL CHARACTERISTICS ............................................................................................... 10 THERMAL CHARACTERISTICS............................................................................................ 10 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ................................................. 11 2 PIN DESCRIPTION ................................................................................................................. 13 3 TYPICAL CONNECTION DIAGRAM ....................................................................................... 14 4 APPLICATIONS ....................................................................................................................... 15 4.1 Single, Double, and Quad Speed Modes ......................................................................... 15 4.2 Operation as Either a Clock Master or Slave ................................................................... 15 4.2.1 Operation as a Clock Master ............................................................................... 16 4.2.2 Operation as a Clock Slave ................................................................................. 16 4.2.3 Master Clock ....................................................................................................... 17 4.3 Serial Audio Interface ....................................................................................................... 17 4.4 Power-up Sequence ........................................................................................................ 18 4.5 Analog Connections ......................................................................................................... 18 4.6 Grounding and Power Supply Decoupling ....................................................................... 18 4.7 Synchronization of Multiple Devices ................................................................................ 19 4.8 Capacitor Size on the Reference Pin (FILT+) .................................................................. 19 5 PARAMETER DEFINITIONS ................................................................................................... 20 6 PACKAGE DIMENSIONS ....................................................................................................... 21 7. REVISION HISTORY .............................................................................................................. 22
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com/
IMPORTANT NOTICE
LEGAL NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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LIST OF FIGURES
Figure 1. Single Speed Stopband Rejection .................................................................................. 8 Figure 2. Single Speed Stopband Rejection (detail) ...................................................................... 8 Figure 3. Single Speed Transition Band (detail) ............................................................................ 8 Figure 4. Single Speed Passband Ripple ...................................................................................... 8 Figure 5. Double Speed Stopband Rejection ................................................................................. 8 Figure 6. Double Speed Stopband Rejection (detail) ..................................................................... 8 Figure 7. Double Speed Transition Band (detail) ........................................................................... 9 Figure 8. Double Speed Passband Ripple ..................................................................................... 9 Figure 9. Quad Speed Stopband Rejection ................................................................................... 9 Figure 10. Quad Speed Stopband Rejection (detail) ..................................................................... 9 Figure 11. Quad Speed Transition Band (detail) ............................................................................ 9 Figure 12. Quad Speed Passband Ripple ...................................................................................... 9 Figure 13. Master Mode, Left Justified SAI .................................................................................. 12 Figure 14. Slave Mode, Left Justified SAI .................................................................................... 12 Figure 15. Master Mode, I2S SAI ................................................................................................. 12 Figure 16. Slave Mode, I2S SAI ................................................................................................... 12 Figure 17. Typical Connection Diagram ....................................................................................... 14 Figure 18. CS5342 Master Mode Clocking .................................................................................. 16 Figure 19. Left-Justified Serial Audio Interface ............................................................................ 17 Figure 20. I2S Serial Audio Interface ............................................................................................ 17 Figure 21. CS5342 Recommended Analog Input Buffer .............................................................. 18 Figure 22. CS5342 THD+N versus Frequency ............................................................................ 19
LIST OF TABLES
Table 1. Speed Modes and the Associated Output Sample Rates (Fs)........................................ 15 Table 2. CS5342 Mode Control..................................................................................................... 15 Table 3. Master Clock (MCLK) Ratios........................................................................................... 17 Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates .......................... 17 Table 5. Revision History .............................................................................................................. 22
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1 CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TA = 25C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.) Parameter Power Supplies (Notes 2, 3) Analog Digital Logic Commercial (-CZZ) Symbol VA VD VL TAC Min 3.14 3.14 2.38 -10 Typ (Note 1) 3.3 3.3 Max 5.25 5.25 5.25 70 Unit V V V C
Ambient Operating Temperature
Notes: 1. This part is specified at typical analog voltages of 3.3 V and 5.0 V. See Analog Characteristics (CS5342CZZ) below for details. 2. In Quad-Speed Slave Mode, the CS5342 is only specified for operation with VA and VD at 5 V, 5%.
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 3) Parameter DC Power Supplies: Analog Logic Digital (Note 4) (Note 5) (Note 5) Symbol VA VL VD Iin VIN VIND TA Tstg Min -0.3 -0.3 -0.3 GND-0.7 -0.7 -50 -65 Max +6.0 +6.0 +6.0 10 VA+0.7 VL+0.7 +95 +150 Units V V V mA V V C C
Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature
Notes: 3. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 4. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SRC latch-up. 5. The maximum over/under voltage is limited by the input current.
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ANALOG CHARACTERISTICS (CS5342-CZZ) Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.
Parameter VA = 3.3 V Single Speed Mode Fs = 48 kHz Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise (Note 6) -1 dB -20 dB -60 dB Double Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 6) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Quad Speed Mode (Note 2) Fs = 192 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 6) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB VA = 5.0 V Single Speed Mode Fs = 48 kHz Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise (Note 6) -1 dB -20 dB -60 dB Double Speed Mode Fs = 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 6) -1 dB -20 dB -60 dB -1 dB Symbol Min Typ Max Unit
96 93 THD+N 96 93 THD+N 96 93 THD+N -
102 99 -95 -79 -39 102 99 96 -95 -79 -39 -87 102 99 96 -95 -79 -39 -87
-89 -89 -89 -
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
99 96 THD+N 99 96 THD+N -
105 102 -98 -82 -42 105 102 99 -98 -82 -42 -95
-92 -92 -
dB dB dB dB dB dB dB dB dB dB dB dB
40 kHz bandwidth
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Quad Speed Mode (Note 2) Dynamic Range Fs = 192 kHz A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 6) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Dynamic Performance for All Modes Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Error
99 96 THD+N -3 0.54*VA 18
105 102 99 -98 -82 -42 -95 90 0.1 -
-92 3 0.58*VA -
dB dB dB dB dB dB dB dB dB % ppm/C Vpp k
Gain Drift Analog Input Characteristics Full-scale Input Voltage Input Impedance Note: 6. Referred to the typical full-scale input voltage
100
0.56*VA -
6
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DIGITAL FILTER CHARACTERISTICS
Parameter (Note 7) Single Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Double Speed Mode Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Quad Speed Mode (Note 2) Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) High Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time Note: -3.0 dB -0.13 dB @ 20 Hz (Note 7) (Note 7) 1 20 10 105/Fs 0 Hz Hz Deg dB s tgd (-0.1 dB) 0 -0.1 0.5000 60 5/Fs 0.2604 0.058 Fs dB Fs dB s tgd (-0.1 dB) 0 -0.1 0.5604 69 9/Fs 0.4896 0.058 Fs dB Fs dB s tgd (-0.1 dB) 0 -0.1 0.5688 70 12/Fs 0.4896 0.035 Fs dB Fs dB s Symbol Min Typ Max Unit
7. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 1 to 12) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
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0 -10 -2 0
0 -10 -2 0
Amplitude (dB)
- 50 -6 0 - 70 -8 0 -9 0 - 10 0 - 110 - 12 0 - 13 0 - 14 0 0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0
Amplitude (dB)
-3 0 -4 0
-3 0 -4 0 - 50 -6 0 - 70 -8 0 -9 0 - 10 0 - 110 - 12 0 - 13 0 - 14 0 0 .4 0 0 .4 2 0 .4 4 0 .4 6 0 .4 8 0 .50 0 .52 0 .54 0 .56 0 .58 0 .6 0
Fr e qu e n cy (no r m aliz e d to Fs )
Fr e q ue n cy (no r m aliz e d to Fs )
Figure 1. Single Speed Stopband Rejection
Figure 2. Single Speed Stopband Rejection (detail)
0 -1 -2
0 .10 0 .0 8 0 .0 6
Amplitude (dB)
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0 .4 5 0 .4 6 0 .4 7 0 .4 8 0 .4 9 0 .5 0 .51 0 .52 0 .53 0 .54 0 .55
0 .0 4 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -0 .0 6 -0 .0 8 -0 .10 0 0 .0 5 0 .1 0 .15 0 .2 0 .2 5 0 .3 0 .3 5 0 .4 0 .4 5 0 .5
Fr e qu e n cy (n or m aliz e d to Fs )
Fr e qu e n cy (n or m aliz e d to Fs )
Figure 3. Single Speed Transition Band (detail)
Figure 4. Single Speed Passband Ripple
0 -10 -2 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0
0 -10 -2 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 0 .4 0
Amplitude (dB)
Amplitude (dB)
0 .4 2
0 .4 4
0 .4 6
0 .4 8
0 .50
0 .52
0 .54
0 .56
0 .58
0 .6 0
Fr e qu e n cy (no r m aliz e d to Fs )
Fr e q ue n cy (no r m aliz e d to Fs )
Figure 5. Double Speed Stopband Rejection
Figure 6. Double Speed Stopband Rejection (detail)
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0 -1 -2 0 .10 0 .0 8 0 .0 6
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0 .4 6 0 .4 7 0 .4 8 0 .4 9 0 .50 0 .51 0 .52
Amplitude (dB)
0 .0 4 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -0 .0 6 -0 .0 8 -0 .10 0 .0 0 0 .0 5 0 .10 0 .15 0 .2 0 0 .2 5 0 .3 0 0 .3 5 0 .4 0 0 .4 5 0 .50
Fr e qu e n cy (n or m aliz e d to Fs )
Fr e qu e n cy (n or m aliz e d to Fs )
Figure 7. Double Speed Transition Band (detail)
Figure 8. Double Speed Passband Ripple
0 -10 -2 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0
0 -10 -2 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Amplitude (dB)
Fr e qu e n cy (no r m aliz e d to Fs )
Amplitude (dB)
Fr e qu e n cy (no r m aliz e d to Fs )
Figure 9. Quad Speed Stopband Rejection
Figure 10. Quad Speed Stopband Rejection (detail)
0 -1 -2 0 .10 0 .0 8 0 .0 6
Amplitude (dB)
-3
Amplitude (dB)
0 .15 0 .2 0 0 .2 5 0 .3 0 0 .3 5 0 .4 0 0 .4 5 0 .50
-4 -5 -6 -7 -8 -9 -10 0 .10
0 .0 4 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -0 .0 6 -0 .0 8
Fr e qu e n cy (n or m aliz e d to Fs )
-0 .10 0 .0 0 0 .0 3 0 .0 5 0 .0 8 0 .10
0 .13
0 .15 0 .18 0 .2 0 0 .2 3 0 .2 5 0 .2 8
Fr e qu e ncy (n or m aliz e d to Fs )
Figure 11. Quad Speed Transition Band (detail)
Figure 12. Quad Speed Passband Ripple
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DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to 0 V.
MCLK=18.432 MHz; Master Mode; refer to Note 2) Parameter DC Power Supplies: Positive Analog Positive Digital Positive Logic VA = 5 V VA = 3.3 V VL,VD = 5 V VL,VD = 3.3 V VA = 5 V VL,VD=5 V VL, VD, VA = 5 V VL, VD, VA = 3.3 V (Power-Down Mode) (1 kHz) (Note 9) Symbol VA VD VL IA IA ID ID IA ID PSRR Min 3.14 3.14 2.38 Typ 21 18.2 15 9 1.5 0.4 180 90 9.5 65 VA/2 25 VA 36 0.01 Max 5.25 5.25 5.25 23.1 20 16.5 10 198 100 Unit V V V mA mA mA mA mA mA mW mW mW dB V
Power Supply Current (Normal Operation)
Power Supply Current (Power-down Mode) (Note 8) Power Consumption (Normal Operation) Power Supply Rejection Ratio VQ Nominal Voltage Output Impedance
k
V
Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink
k
mA
Notes: 8. Power-down Mode is defined as RST = Low with all clocks and data lines held static. 9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the "Typical Connection Diagram".
DIGITAL CHARACTERISTICS
Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage at Io = 100 A Low-level Output Voltage at Io =100 A Input Leakage Current (% of VL) (% of VL) (% of VL) (% of VL) Symbol VIH VIL VOH VOL Iin Min 70% 70% Typ Max 30% 15% 10 Units V V V V A
THERMAL CHARACTERISTICS
Parameter Allowable Junction Temperature Junction-to-ambient Thermal Impedance Symbol Min Typ 75 Max 135 Unit C C/W
JA
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SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V;
Logic "1" = VL, C L = 20 pF) Parameter MCLK Specifications MCLK Period MCLK Pulse Duty Cycle Master Mode SCLK falling to LRCK SCLK falling to SDOUT valid SCLK Duty Cycle Single-Speed Double-Speed Quad-Speed tmslr tsdo -20 50 50 33 20 32 ns ns % % % tclkw 26 52 40 31 1303 60 ns ns % Symbol Min Typ Max Unit
Slave Mode Single Speed* LRCK Duty Cycle SCLK Period SCLK Duty Cycle SDOUT valid before SCLK rising SDOUT valid after SCLK rising SCLK falling to LRCK edge Double Speed* LRCK Duty Cycle SCLK Period (Note 9) SCLK Duty Cycle SDOUT valid before SCLK rising SDOUT valid after SCLK rising SCLK falling to LRCK edge Quad Speed* (Note 2) LRCK Duty Cycle SCLK Period (Note 9) SCLK Duty Cycle SDOUT valid before SCLK rising SDOUT valid after SCLK rising SCLK falling to LRCK edge tstp thld tslrd tsclkw 40 104 40 10 5 -8 60 50 8 % ns % ns ns ns tstp thld tslrd tsclkw 40 193 45 10 5 -20 60 55 20 % ns % ns ns ns tstp thld tslrd tsclkw 40 290 45 10 5 -20 60 55 20 % ns % ns ns ns
* For a description of Speed Modes, please refer to Table 1 on page 15 Notes: 9. SCLK must be derived synchronously from MCLK and the ratio of SCLK/LRCK must be equal to 48.
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LRCK output
tmslr
LRCK input
t slrd t sclkw
SCLK output
tsdo
SCLK input
t stp thld
SDOUT
MSB
MSB-1
SDOUT
MSB
MSB-1
Figure 13. Master Mode, Left Justified SAI
Figure 14. Slave Mode, Left Justified SAI
LRCK output
tmslr
LRCK input
t slrd tsclkw
SCLK output
t sdo
SCLK input
t stp thld
SDOUT
MSB
MSB-1
SDOUT
MSB
Figure 15. Master Mode, I2S SAI
Figure 16. Slave Mode, I2S SAI
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2 PIN DESCRIPTION
M0 MCLK VL SDOUT GND VD SCLK LRCK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 M1 FILT+ REFGND VA AINR VQ AINL RST
Pin Name
M0 M1 MCLK VL SDOUT GND VD SCLK LRCK RST AINL AINR VQ VA REFGND FILT+
# 1 16 2 3 4 5 6 7 8 9 10 12 11 13 14 15
Pin Description
Mode Selection (Input) - Determines the operational mode of the device. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Logic Power (Input) - Positive power for the digital input/output. Serial Audio Data Output (Output) - Output for two's complement serial audio data. Ground (Input) - Ground reference. Must be connected to analog ground. Digital Power (Input) - Positive power supply for the digital section. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Reset (Input) - The device enters a low power mode when low. Analog Input (Input) - The full scale analog input level is specified in the Analog Characteristics specification table. Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. Analog Power (Input) - Positive power supply for the analog section. Reference Ground (Output) - Ground reference for the internal sampling circuits. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
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3 TYPICAL CONNECTION DIAGRAM
3.3V to 5V
4
+
1 F
0.1 F
2
0.1 F
+
1 F
2.5V to 5V
3.3V to 5V
4
+
1 F
0.1 F
5.1
0.1 F
VA FILT+ 1 F
3
VD
VL
+
0.1 F REFGND 0.1 F VQ RST M0 M1 VL or GND 10 k A INL
1
+
1 F
CS5342 A/D CONVERTER
Power Down and Mode Settings
Analog Input Buffer Figure 15 AI NR
SDOUT
Audio Data Processor
MCLK LRCK SCLK
1 Pull-up to VL for I2S Pull-down to GND for LJ
Timing Logic and Clock
GND
2 Resistor may only be used if VD is derived from VA. If used, do not drive any other logic from VD
Capacitor value affects low frequency distortion performance as described in Section 4.8
4
3
See Note 2 on page 4
Figure 17. Typical Connection Diagram
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4 APPLICATIONS 4.1 Single, Double, and Quad Speed Modes
The CS5342 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be determined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.
Speed Mode Single Speed Mode Double Speed Mode Quad Speed Mode
MCLK/LRCK Ratio 768x 384x 384x 192x 192x 96x*
Output Sample Rate Range (kHz) 43 - 54 2 - 54 86 - 108 50 - 108 172 - 200 100 - 200
* Quad Speed Mode, 96x only available in Master Mode. Table 1. Speed Modes and the Associated Output Sample Rates (Fs)
4.2
Operation as Either a Clock Master or Slave
The CS5342 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK pins are outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the LRCK and SCLK pins are inputs and require the left/right and serial clocks to be externally generated. The selection of clock master or slave is made via the Mode pins as shown in Table 2.
M1 (Pin 16) 0 0 1 1
M0 (Pin 1) 0 1 0 1
Clock Clock Clock Clock
MODE Master, Single Speed Mode Master, Double Speed Mode Master, Quad Speed Mode Slave, All Speed Modes
Table 2. CS5342 Mode Control
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4.2.1 Operation as a Clock Master
As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 18.
/ 256 / 128 / 64 / 1.5 MCLK /3 1 /4 Auto-Select /2 /1 0
Single Speed Double Speed Quad Speed
00 01 10
LRCK Output (Equal to Fs)
M[1:0]
Single Speed Double Speed Quad Speed
00 01 10
SCLK Output
Figure 18. CS5342 Master Mode Clocking
4.2.2
Operation as a Clock Slave
LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and equal to 48x Fs or 64x Fs in Single-Speed Mode. In DoubleSpeed and Quad-Speed Modes the serial clock must be derived synchronously from the master clock and equal to 48x Fs. Additionally, Quad-Speed Slave Mode is only specified for operation with a VA and VD at 5 V, 5%. A unique feature of the CS5342 is the automatic selection of either Single, Double or Quad speed mode when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are not supported when operating with a fast MCLK (768x, 384x, and 192x for Single, Double, and Quad Speed Modes respectively). Please refer to Table 1 on page 15 for supported sample rate ranges.
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4.2.3 Master Clock
The CS5342 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. There is also an internal MCLK divider which is automatically activated based on the frequency of the MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required. Table 4 lists some common audio output sample rates and the required MCLK frequency. Please note that not all of the listed sample rates are supported when operating with a fast MCLK (768x, 384x, 192x for Single, Double, and Quad Speed Modes respectively). Single Speed Mode MCLK/LRCK Ratio 384x, 768x * Quad Speed, 96x only available in Master Mode. Table 3. Master Clock (MCLK) Ratios Double Speed Mode 192x, 384x Quad Speed Mode 96x*, 192x
SAMPLE RATE (kHz) 32 44.1 48 64 88.2 96 192
MCLK (MHz) 12.288 16.9344 33.8688 18.432 36.864 12.288 16.9344 33.8688 18.432 36.864 36.864
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates
4.3
Serial Audio Interface
The CS5342 supports both I2S and Left Justified serial audio formats. Upon start-up, the CS5342 will detect the logic level on SDOUT (pin 4). A 10 k pull-up resistor to VL is needed to select I2S format, and a 10 k pull-down resistor to GND is needed to select Left Justified format. Please see Figures 13 through 16 on page 12, for more information on the required timing for the two serial audio interface formats.
LRCK Left Channel Right Channel
SCLK
SDATA
23 22
9
8
7
6
5
4
3
21
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 19. Left-Justified Serial Audio Interface
LRCK
Left Channel
Right Channel
SCLK
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 20. I2S Serial Audio Interface
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CS5342
4.4 Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues.
4.5
Analog Connections
The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are multiples of the input sampling frequency (n x 6.144 MHz), where n=0,1,2,... Refer to Figure 15 which shows the suggested filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity.
634 VA 470 pF COG 4.7 uF AINL 100 k 100 k 91 CS5342 AINL 2200 pF
VA
4.7 uF AINL
100 k 91 CS5342 AINL 100 k COG 470 pF 2200 pF
634
Figure 21. CS5342 Recommended Analog Input Buffer
4.6
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5342 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 17 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and REF_GND. The CDB5342 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
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CS5342
4.7 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5342's in the system.
4.8
Capacitor Size on the Reference Pin (FILT+)
The CS5342 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this decoupling capacitor will affect the low frequency distortion performance as shown in Figure 22, with larger capacitor values used to optimize low frequency distortion performance. The THD+N curves in Figure 22 were measured with VA = VD = VL = 5 V in Single-Speed Master Mode using a 1 kHz input tone of magnitude -1 dB Full-Scale.
1 uF
2.2 uF
3.3 uF
4.7 uF 5.6 uF 6.8 uF
10 uF
22 uF 47 uF
100 uF
Figure 22. CS5342 THD+N versus Frequency
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CS5342
5 PARAMETER DEFINITIONS
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
Dynamic Range
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CS5342
6 PACKAGE DIMENSIONS
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e b2 SIDE VIEW
123
END VIEW
SEATING PLANE
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.03346 0.00748 0.193 0.248 0.169 -0.020 0
INCHES NOM -0.004 0.0354 0.0096 0.1969 0.2519 0.1732 0.026 BSC 0.024 4
MAX 0.043 0.006 0.037 0.012 0.201 0.256 0.177 -0.028 8
MIN -0.05 0.85 0.19 4.90 6.30 4.30 -0.50 0
MILLIMETERS NOM --0.90 0.245 5.00 6.40 4.40 0.065 BSC 0.60 4
NOTE MAX 1.10 0.15 0.95 0.30 5.10 6.50 4.50 -0.70 8
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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CS5342
7. REVISION HISTORY
Date April 2003 July 2003 August 2004 Changes -Initial Advance Release. -Modify serial port timing specs. -Add Applications section on speed mode detect. -Change 2700 pF capacitors to 2200 pF in analog input buffer diagram. -Update Output Sample Range table. -Add new Applications section about capacitor on FILT+ pin. -Correct Max MCLK period under "Switching Characteristics." -Replace MCLK low/high timing specifications with duty cycle specification. -Redefine slave mode timing specifications under "Switching Characteristics." -Add requirement of SCLK/LRCK = 48x in Double and Quad Speed Modes. -Increase minimum VL specification from 1.7 V to 2.38 V. -Specify VA and VD at 5 V, 5% for Quad-Speed Slave Mode. -Reduce gain error specification under Analog Characteristics. -Improve minimum and maximum specifications for full-scale input voltage. -Initial Preliminary Release. Update to include lead-free device ordering information.
Table 5. Revision History
Release A1 A2 PP1
PP2
Aug 2004
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DS608PP2

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